Publicaciones

Aguado-Puig, Q., Marco-Sola, S., Moure, J., Castells-Rufas, D., Alvarez, L., Espinosa, A., & Moreto, M. (2022). Accelerating Edit-Distance Sequence Alignment on GPU using the Wavefront Algorithm. IEEE access.

Martí Caro, Hamid Tabani, and Jaume Abella. 2022. At-scale assessment of weight clustering for energy-efficient object detection accelerators. In Proceedings of the 37th ACM/SIGAPP Symposium on Applied Computing (SAC '22). Association for Computing Machinery, New York, NY, USA, 530–533. https://doi.org/10.1145/3477314.3507161

D. Castells-Rufas, S. Marco-Sola, J. C. Moure, Q. Aguado and A. Espinosa, "FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS," in IEEE Access, vol. 10, pp. 22079-22100, 2022, doi: 10.1109/ACCESS.2022.3153032.

D Castells-Rufas, S. Marco-Sola, Q. Aguado-Puig, A. Espinosa-Morales, J.C. Moure, L. Alvarez, and M. Moretó. “OpenCL-based FPGA accelerator for semi-global approximate string matching using diagonal bit-vectors”. In 2021 31st International Conference on Field-Programmable Logic and Applications (FPL) (pp. 174-178). IEEE..

E. Rodríguez, B. Otero, N. Gutiérrez and R. Canal, "A Survey of Deep Learning Techniques for Cybersecurity in Mobile Networks," in IEEE Communications Surveys & Tutorials, doi: 10.1109/COMST.2021.3086296.

Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, et all. "Adaptable Register File Organization for Vector Processors", in the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2022), <https://arxiv.org/abs/2111.05301>

A. Haghi, S. Marco-Sola, L. Alvarez, D. Diamantopoulos, C. Hagleitner and M. Moreto, "An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment," 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021, pp. 151-159, doi: 10.1109/FPL53798.2021.00033.

A. Monemi, I. Pérez, N. Leyva, E. Vallejo, R. Beivide and M. Moretó, "PlugSMART: a pluggable open-source module to implement multihop bypass in Networks-on-Chip," 2021 15th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2021, pp. 41-48.

Cristóbal Ramírez, César Alejandro Hernández, Oscar Palomar, Osman Unsal, Marco Antonio Ramírez, and Adrián Cristal. 2020. A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. ACM Trans. Archit. Code Optim. 17, 4, Article 38 (November 2020), 30 pages. DOI:https://doi.org/10.1145/3422667

J. Abella et al., "An Academic RISC-V Silicon Implementation Based on Open-Source Components," 2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain, 2020, pp. 1-6, doi: 10.1109/DCIS51330.2020.9268664.