FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS

Tipus de publicació

Article in journal

Autors

David Castells-Rufas, Santiago Marco-Sola, Juan Carlos Moure, Quim Aguado, Antonio Espinosa

Editor

Institute of Electrical and Electronics Engineers

Any de Publicació

2022

cita bibliogràfica

D. Castells-Rufas, S. Marco-Sola, J. C. Moure, Q. Aguado and A. Espinosa, "FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS," in IEEE Access, vol. 10, pp. 22079-22100, 2022, doi: 10.1109/ACCESS.2022.3153032.

Enllaç a la publicació

https://ieeexplore.ieee.org/document/9718100

DOI

10.1109/ACCESS.2022.3153032