Publicacions

Publication in Conference Proceedings/Workshop

D. Castells-Rufas, S. Marco-Sola, J. C. Moure, Q. Aguado and A. Espinosa, "FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS," in IEEE Access, vol. 10, pp. 22079-22100, 2022, doi: 10.1109/ACCESS.2022.3153032.


DOI: 10.1109/ACCESS.2022.3153032
Publication in Conference Proceedings/Workshop

David Castells-Rufas, Santiago Marco-Sola, Juan Carlos Moure, Quim Aguado, Antonio Espinosa, "FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS", Access IEEE, vol. 10, pp. 22079-22100, 2022.


DOI: 10.1109/FPL53798.2021.00036
Article in journal

E. Rodríguez, B. Otero, N. Gutiérrez and R. Canal, "A Survey of Deep Learning Techniques for Cybersecurity in Mobile Networks," in IEEE Communications Surveys & Tutorials, doi: 10.1109/COMST.2021.3086296.


DOI: 10.1109/COMST.2021.3086296
Publication in Conference Proceedings/Workshop

Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, et all. "Adaptable Register File Organization for Vector Processors", in the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2022), <https://arxiv.org/abs/2111.05301>


DOI: https://doi.org/10.48550/arXiv.2111.05301
Publication in Conference Proceedings/Workshop

A. Haghi, S. Marco-Sola, L. Alvarez, D. Diamantopoulos, C. Hagleitner and M. Moreto, "An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment," 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021, pp. 151-159, doi: 10.1109/FPL53798.2021.00033.


DOI: 10.1109/FPL53798.2021.00033
Article in journal

Cristóbal Ramírez, César Alejandro Hernández, Oscar Palomar, Osman Unsal, Marco Antonio Ramírez, and Adrián Cristal. 2020. A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. ACM Trans. Archit. Code Optim. 17, 4, Article 38 (November 2020), 30 pages. DOI:https://doi.org/10.1145/3422667


DOI: 10.1145/3422667
Publication in Conference Proceedings/Workshop

J. Abella et al., "An Academic RISC-V Silicon Implementation Based on Open-Source Components," 2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain, 2020, pp. 1-6, doi: 10.1109/DCIS51330.2020.9268664.


DOI: 10.1109/DCIS51330.2020.9268664
Publication in Conference Proceedings/Workshop

Doblas, M. [et al.]. Enabling hardware randomization across the cache hierarchy in Linux-Class processors. A: Workshop on Computer Architecture Research with RISC-V. "Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020): Virtual Workshop, Friday, May 29th, 2020: co-located with ISCA 2020". 2020, p. 1-7.


Article in journal

Santiago Marco-Sola, Juan Carlos Moure, Miquel Moreto, Antonio Espinosa, Fast gap-affine pairwise alignment using the wavefront algorithm, Bioinformatics, , btaa777, DOI: 10.1093/bioinformatics/btaa777


DOI: 10.1093/bioinformatics/btaa777