News

Kameleon, a RISC-V Based 2-core Multi-accelerator Academic SoC
Kameleon, the fourth generation of the Lagarto processor series, submitted for fabrication via Europractice
DRAC celebrates its last meeting with the RISC-V community highlighting the results obtained in the project and the tools to address current and future challenges.
DRAC Final Event
[Tech] New results in cache side-channel attacks and countermeasures
[Tech] Adding virtualization hardware support to Sargantana processor
[Tech] Development of a specific test platform for Sargantana
[Tech] Accelerating edit-distance sequence alignment on GPU using the Wavefront algorithm
Fifth General Meeting
[Tech] A Security Model for Randomization-based Protected Caches