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Designing RISC-V-based Accelerators for next generation Computers
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News

01/12/2022
DRAC Final Event
25/11/2022
[Tech] New results in cache side-channel attacks and countermeasures
06/10/2022
[Tech] Adding virtualization hardware support to Sargantana processor
27/09/2022
[Tech] Development of a specific test platform for Sargantana
28/07/2022
[Tech] Accelerating edit-distance sequence alignment on GPU using the Wavefront algorithm
13/07/2022
Fifth General Meeting
07/06/2022
[Tech] A Security Model for Randomization-based Protected Caches
25/04/2022
[Tech] What’s inside the Sargantana chip?
11/04/2022
[Tech] Sargantana, the third generation of the Lagarto processor series, submitted for fabrication via Europractice
25/02/2022
Fourth General meeting

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LOGO DRU + EU

 

The DRAC project with -file number 001-P-001723- has been 50% co-financed with € 2,000,000.00 by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020, with the support of Generalitat of Catalonia.

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