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Designing RISC-V-based Accelerators for next generation Computers
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News

27/07/2023
Kameleon, a RISC-V Based 2-core Multi-accelerator Academic SoC
20/06/2023
Kameleon, the fourth generation of the Lagarto processor series, submitted for fabrication via Europractice
30/01/2023
DRAC celebrates its last meeting with the RISC-V community highlighting the results obtained in the project and the tools to address current and future challenges.
01/12/2022
DRAC Final Event
25/11/2022
[Tech] New results in cache side-channel attacks and countermeasures
06/10/2022
[Tech] Adding virtualization hardware support to Sargantana processor
27/09/2022
[Tech] Development of a specific test platform for Sargantana
28/07/2022
[Tech] Accelerating edit-distance sequence alignment on GPU using the Wavefront algorithm
13/07/2022
Fifth General Meeting
07/06/2022
[Tech] A Security Model for Randomization-based Protected Caches

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LOGO DRU + EU

 

The DRAC project with -file number 001-P-001723- has been 50% co-financed with € 2,000,000.00 by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020, with the support of Generalitat of Catalonia.

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  • Home
  • About DRAC
  • Consortium
    • Partners
    • Collaborators
    • Advisory Board
  • Results
    • Publicaciones
    • Deliverables
  • Media
    • News
    • Events
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    • Press clippings
  • Contact