Skip to main content
Català
Castellano
English
Designing RISC-V-based Accelerators for next generation Computers
Menu
Home
About DRAC
Consortium
Partners
Collaborators
Advisory Board
Results
Publicaciones
Deliverables
Media
News
Events
Branding
Press clippings
Contact
News
11/04/2022
[Tech] Sargantana, the third generation of the Lagarto processor series, submitted for fabrication via Europractice
15/01/2022
[Tech] FPGA Acceleration of Pre-alignment Filters for Short read mapping with HLS
20/12/2021
[Tech] A Low-Power High-Resolution Switched-Capacitor Delta-Sigma ADC IP for Edge-Computing in IoT Applications
16/11/2021
[Tech] Lagarto KA: The High Performance Core for DRAC
17/10/2021
[Tech] An HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
14/10/2021
We approach DRAC to the industry
15/09/2021
[Tech] Extending RISC-V core capabilities with virtualization support
23/07/2021
Third General Online meeting
16/07/2021
[Tech] Design flow: logic and physical synthesis
15/06/2021
[Tech] An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
Pagination
Current page
1
Page
2
Page
3
Next page
››
Last page
Last »
Home
About DRAC
Consortium
Partners
Collaborators
Advisory Board
Results
Publicaciones
Deliverables
Media
News
Events
Branding
Press clippings
Contact