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Designing RISC-V-based Accelerators for next generation Computers
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News

11/04/2022
[Tech] Sargantana, the third generation of the Lagarto processor series, submitted for fabrication via Europractice
15/01/2022
[Tech] FPGA Acceleration of Pre-alignment Filters for Short read mapping with HLS
20/12/2021
[Tech] A Low-Power High-Resolution Switched-Capacitor Delta-Sigma ADC IP for Edge-Computing in IoT Applications
16/11/2021
[Tech] Lagarto KA: The High Performance Core for DRAC
17/10/2021
[Tech] An HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
14/10/2021
We approach DRAC to the industry
15/09/2021
[Tech] Extending RISC-V core capabilities with virtualization support
23/07/2021
Third General Online meeting
16/07/2021
[Tech] Design flow: logic and physical synthesis
15/06/2021
[Tech] An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment

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LOGO DRU + EU

 

The DRAC project with -file number 001-P-001723- has been 50% co-financed with € 2,000,000.00 by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020, with the support of Generalitat of Catalonia.

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  • Home
  • About DRAC
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    • Collaborators
    • Advisory Board
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    • Publicaciones
    • Deliverables
  • Media
    • News
    • Events
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    • Press clippings
  • Contact