News

[Tech] An HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
[Tech] Lagarto KA: The High Performance Core for DRAC
[Tech] Extending RISC-V core capabilities with virtualization support
Third General Online meeting
[Tech] Design flow: logic and physical synthesis
[Tech] An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
[Tech] New PLL for DVINO processor, a new member of the Lagarto RISC-V family
[Tech] DVINO, the second generation of the Lagarto processor series, submitted for fabrication via Europractice
2021 Workshop on Negative results, Opportunities, Perspectives, and Experiences
[Tech] Post-Quantum Security in the DRAC Project