News

[Tech] What’s inside the Sargantana chip?
[Tech] Sargantana, the third generation of the Lagarto processor series, submitted for fabrication via Europractice
Fourth General meeting
[Tech] FPGA Acceleration of Pre-alignment Filters for Short read mapping with HLS
[Tech] A Low-Power High-Resolution Switched-Capacitor Delta-Sigma ADC IP for Edge-Computing in IoT Applications
[Tech] Lagarto KA: The High Performance Core for DRAC
[Tech] An HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
We approach DRAC to the industry
[Tech] Extending RISC-V core capabilities with virtualization support
Third General Online meeting