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Designing RISC-V-based Accelerators for next generation Computers
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News

16/07/2021
[Tech] Design flow: logic and physical synthesis
15/06/2021
[Tech] An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
07/06/2021
[Tech] New PLL for DVINO processor, a new member of the Lagarto RISC-V family
18/05/2021
[Tech] DVINO, the second generation of the Lagarto processor series, submitted for fabrication via Europractice
20/04/2021
2021 Workshop on Negative results, Opportunities, Perspectives, and Experiences
18/03/2021
[Tech] Post-Quantum Security in the DRAC Project
01/03/2021
DRAC holds its second online general meeting
15/02/2021
[Tech] Low power accelerator for autonomous driving based on approximation principles
15/01/2021
[Tech] The integration, design and manufacture of prototypes (tape-out) of DRAC processors, and the development of test platforms for these processors
21/12/2020
[Tech] Fast gap-affine pairwise alignment using the wavefront algorithm

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LOGO DRU + EU

 

The DRAC project with -file number 001-P-001723- has been 50% co-financed with € 2,000,000.00 by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020, with the support of Generalitat of Catalonia.

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  • Home
  • About DRAC
  • Consortium
    • Partners
    • Collaborators
    • Advisory Board
  • Results
    • Publicaciones
    • Deliverables
  • Media
    • News
    • Events
    • Branding
    • Press clippings
  • Contact