Deliverables

ID TITLE STATUS
E1.1 Document of the initial design of the processor and the interfaces between the different components (memory hierarchy, core and accelerators) In development
E1.2 Processor design final document In development
E2.1 Analysis of post-quantum cryptographic schemes In development
E2.2 Analysis of post-quantum cryptographic schemes. RISC-V extensions for virtualization and acceleration of post-quantum schemas In development
E2.3 Analysis of side channel attacks In development
E2.4 AAnalysis of post-quantum cryptographic schemes (second version). RISC-V extensions for schema virtualization and acceleration In development
E3.1 Report on the performance of applications and analysis pipelines in computer systems In development
E3.2 Development of an architecture simulator In development
E3.3 Report on the performance of the final design and adaptation of pipelines to new architectures In development
E4.1 Automotive Software Requirements Download
E4.2 Specification, design and implementation of the automotive accelerator In development
E4.3 Final implementation and evaluation of the final design of the automotive accelerator In development
E5.1 Report on target technology In development
E5.2 Reviewable run forecast calendar Internal document
E5.3 Final report of participation in each run In development
E5.4 Report on the development of the test platform and the characterization of the processor chips In development
E6.1 Dissemination plan Download
E6.2 Explotation plan In development
E6.3 First dissemination and exploitation monitoring report In development
E6.4 Second dissemination and exploitation monitoring report In development
E6.5 Third dissemination and exploitation monitoring report In development